In a dynamic RAM (referred to as DRAM, hereinafter), a plurality of sense amplifiers each as shown in FIG. 6 are incorporated to amplify the information signals stored in the memory cells to a logical level, respectively. In FIG. 6, a memory cell is composed of a capacitor and a gate transistor. One end of this gate transistor is connected to a bit line BL or/BL, and the other end thereof is connected to the capacitor. The gate of this transistor is connected to a word line WL. Further, a predetermined voltage V.sub.REF is applied to the other end of this capacitor. When data is written in the memory cell, the word line WL is set to a high potential to turn on the gate transistor, and further the bit line BL is set to a high level potential VDD or a reference potential VSS. The nodes of the memory cell are set to these potentials. Thereafter, the word line WL is set to the reference potential VSS to turn off the transistor, in order that the information can be stored in the memory capacitor as a charge. On the other hand, when the stored information is read out of the memory cell, a control line EQL for precharge is set to a high potential to turn on transistors T5 to T7. When the transistor T5 is turned on, bit lines BL and/BL are connected to each other and therefore equalized at the same potential. A line VBL is connected to one end of each of the two transistors T6 and T7, and a voltage of (1/2) VCC is applied to this line VBL. The bit lines BL and/BL are connected to the other end of each of the two transistors T6 and T7, respectively. Accordingly, the bit line on the L-level side is raised in potential and the bit line on the H-level side is lowered in potential, so that both the potentials of the bit lines BL and/BL are set to the same potential of (1/2) VCC. Thereafter, the line EQL is set to a low level to turn off the transistors T5 to T7. Further, the word line is activated, so that the bit lines potentials change according to the status of the memory cell. These small signals of the bit lines are amplified differentially by lowering the potential at the node/SAN of the common sources of two cross-coupled nMOS transistors T1 and. T2. The potential at the node/SAN is set to VSS and the potential at the common node SAP of two cross-coupled pMOS transistors T3 and T4 is pulled up to VDD. Therefore, the potential of a pair of the bit lines swings full between the potentials VDD and VSS, so that the node potential of the memory cell is set to VDD or VSS for refreshment. When a column select signal CSL is supplied, two DQ gates are turned on, so that the logical levels according to the stored information can be derived to the lines DQ and/DQ.
In the DRAM or some of SRAM, the differential type sense amplifier SA as shown in FIG. 5 is provided for each pair of the bit lines. The potential at the common sources of a pair of the nMOS transistors of each sense amplifier SA is derived as the potential VSS from the node /SAN through a transistor QSAN. In the above-mentioned DRAM, however, the number of memory cells connected to the single word line increases with increasing capacity of the transistor DRAM, and thereby the number of bit lines also increases accordingly, thus causing the following problem:
The data read case is taken into account, where a greater part of the cells selected when the word lines WL rise are at a high level and only a small part of the cells are at a low level (referred to as the column bar pattern). When a high or low level cell data is read to one of a pair of the bit lines, the sense amplifier of the DRAM operates in such a way as to decide the high level and the low level, by previously setting the other of the bit lines to an intermediate level between the high level of the cell and the bit line level (from which the low level is read) and further by differentially amplifying the set intermediate level and the level of the line from which the cell data is read.
FIG. 7 shows the potentials of the sense amplifier in the column bar pattern, in which BL and/BL denote a pair of bit lines for a low level read column, BL' and /BL' denote a pair of bit lines for a high level read column, and V.sub.TH denote the potential difference between the gate and source of the transistor. The initial potentials of the low level read column bit lines BL and /BL are V.sub.L and V.sub.R, respectively, and the initial potentials of the high level read column bit lines BL' and /BL' are V.sub.H and V.sub.R, respectively. When the transistor QSAN shown in FIG. 5 operates and thereby the potential at the node/SAN is being pulled to the ground potential VSS, at time T1, the differential amplifications of a greater part of the high level read columns begin; and thereafter at time T2, the differential amplifications of a small part of the low level read columns begin. The reason why there exists a difference in timing of the amplification start time between the two is that there exists a difference in timing between when the potential drops from the high level potential V.sub.H of the bit line pair of the high level read columns to the transistor operating potential V.sub.TH and when the potential drops from the high level potential V.sub.R of the bit line pair of the low level read columns to the transistor operating potential V.sub.TH. Therefore, when the transistor QSAN for activating the sense amplifiers is turned on, charge current flows from all the bit lines of the sense amplifiers activated simultaneously to the coon source node/SAN of the N-channel sense amplifiers.
In this case, at the node /SAN, since the total capacitance of a great number of high level read bit lines increases to such a degree equivalent to a battery cell momentarily, the wiring resistance between the node /SAN and the ground potential VSS or the turn-on resistance of the transistor QSAN cannot be disregarded, with the result that the node/SAN is momentarily clamped at an intermediate level.
Under these conditions, the sense amplifiers of the low level read bit lines to be operated successively are not turned on immediately, so that after the start of the sensing operation, it takes a long time before the potential difference between the gate and the source reaches a sufficient value. As a result, it is necessary to provide a sufficient margin of the bit line sensing operation, thus causing the delay of the access time of the memory device.
To overcome the above-mentioned problem, a circuit for selectively increasing the performance of the sense amplifier by use of a column select line CSL decoded by an column address has been proposed, as shown in FIGS. 12 and 13 (SYMPOSIUM ON VLSI CIRCUIT, 1989 (DIGEST 0F TECHNICAL PAPERS P103 TO 104)).
In the circuit as shown in FIG. 13, N-channel transistors Qn11, Qn12, . . . (the gates of which a supply voltage VCC is applied, respectively) are connected as resistance components between the common source nodes S1, S2, . . . of the sense amplifier circuits SA1, SA2, . . . and a wiring/SANn, respectively. Further, the common source nodes S1, S2, . . . are connected to a reference potential VSS via N-channel transistors Qn21, Qn22, . . . (which operate as switching elements), respectively. Signals CSL1, CSL2, . . . decoded on the basis of the column addresses are applied to the gates of the transistors Qn21, Qn22, . . . to turn on only the transistor of the selected column.
When the transistor QSAN for activating the sense amplifiers are turned on to start the sensing operation, the current of the transistor on the side where the bit line potential is pulled down to a low level is discharged to the reference potential (VSS) terminal via the respective bit line, the transistor Qn11, Qn12, . . . corresponding to the sense amplifier, the wiring/SAN, and the sense amplifier activating transistor QSAN. Therefore, only the transistor Qn21, Qn22, . . connected to the sense amplifier of the selected column is turned on, so that the common source node of the sense amplifier is bypassed to the reference potential (VSS) terminal. In this case, only the parasitic capacitances existing in the selected bit line exert influence upon the above-mentioned current flow and further the potential at the common source node is pulled quickly to the reference potential VSS, so that it is possible to improve the amplification performance selectively.
On the other hand, the circuit configuration and the pattern layout of the semiconductor circuit are now being improved more and more with the advance of the recent multi-wiring technique. FIG. 15 shows an example of the circuit configuration in which the column select lines CSL (the outputs of a column decoder) are arranged in parallel to the bit lines so as to be used in common for a plurality of unit core blocks. In this circuit configuration, since only one column decoder is used for a plurality of unit core blocks, it is possible to reduce the chip area. The unit core block is roughly composed of a cell array section, a sense amplifier section and a DQ gate section for transferring the potential of the selected bit line potential to the DQ line.
Further, in order to reduce the operating current, such a method has been widely used that the memory cells are divided into a plurality of the above-mentioned unit core blocks for reduction of the number of the unit core blocks activated simultaneously (referred to as core block separating operation, hereinafter). In this method, the transistors QSAN for activating the sense amplifiers as shown in FIG. 13 are activated selectively in response to signals .PHI.n decoded on the basis of an row address. When the circuit configuration as shown in FIG. 14 is operated in accordance with the core block separating operation, since the column select line CSL is used in common for a plurality of the unit core blocks, the column select signal CSL is inputted not only to the selected unit core blocks but also to the non-selected unit core blocks.
The problem caused when the column select signal CSL is inputted to the non-selected unit core blocks will be described hereinbelow with reference to FIG. 14. In the non-selected unit core blocks of the semiconductor memory device of bit line (1/2) VCC precharge type, the potentials of the node/SANn, the bit line pair, and the common sources are all set to (1/2) VCC. Therefore, when the selected column select signal CSL rises under these conditions, the transistor Qn21 connected between the common source S1 and the reference potential VSS is turned on in response to the column select signal CSL applied to the gate thereof, to pull down the potential of the common source S1 to the reference potential VSS. In this case, the charge current i2 of the node/SANn and the charge current i3 of the bit line pair BL2 and/BL2 (corresponding to the column to which the non-selected column select signal CSL is inputted) flow, in addition to the charge current il of the bit line pair BL1 and /BL2 (corresponding to the column to which the selected column select signal CSL is inputted). In other words, the current i (i=il+i2+i3) flows through the transistor Qn21, as shown in FIG. 14. Accordingly, first the operating current increases markedly. Secondly, there exists a possibility that the potential of the bit lines BL and/BL to be precharged to the (1/2) VCC is set to a potential lower than the predetermined set potential of (1/2) VCC by the charge currents of i1, i2 and i3. Therefore, the margin of reading "0" from the memory cell is reduced, thus deteriorating the bit line sensing operation.